1. Field of the Invention
This invention relates to a nonvolatile data storage circuit using ferroelectric capacitors, and in particular, to a nonvolatile data storage circuit capable of stabilizing storage operation when the power supply is off.
2. Description of the Related Art
One type of data storage circuit capable of high-speed operation is a latch circuit in which a pair of inverter inputs and outputs are cross-connected. Latch circuits are used as element circuits in flip-flops, or are used as SRAM memory cells. A latch circuit is itself a volatile data storage circuit, in which the held data is lost when the power supply falls. Therefore, nonvolatile data storage circuits have been proposed.
As a nonvolatile data storage circuit, in the non-patent document 1 described below, a device in which ferroelectric capacitors are connected as variable-capacitance capacitors to the storage nodes of a latch circuit forming an SRAM memory cell. FIG. 1 is a circuit diagram of the memory cell. This memory cell comprises a latch circuit 2 in which the input and output terminals of CMOS inverters 1a, 1b are cross-connected; transfer gates 4a, 4b whose gates are connected to the word line WL and either sources or drains are connected to bit lines BL, BLX; and ferroelectric capacitors FC1, FC2 connected to the pair of storage nodes N, NX of the latch circuit 2. The electrodes on the opposite sides of the ferroelectric capacitors FC1, FC2 are connected to the plate line PL.
In the latch circuit 2 comprising the pair of inverters, data is lost when the power supply is interrupted. However, by connecting the ferroelectric capacitors FC1, FC2 to the pair of storage nodes N, NX, the polarization direction of the ferroelectric films in the ferroelectric capacitors can be controlled according to the voltage levels of the storage nodes, and this polarization direction is maintained as a residual polarization even after the power supply falls.
For example, if node N is at L level and node NX is at H level, when the plate line PL is at L level, a voltage is applied to the ferroelectric capacitor FC2, and the polarization direction becomes the direction of the arrow. When the plate line PL is driven to H level, a voltage is applied in the reverse direction to the ferroelectric capacitor FC1, and the polarization direction becomes the opposite direction. This polarization direction is maintained even if the power supply falls, due to the hysteresis characteristic of the ferroelectric film. The above operation associated with the plate line is called a store operation.
When the power supply is turned on, the power supply voltage VDD gradually rises; but due to differences in the polarization direction, the capacitances of the ferroelectric capacitors as seen from nodes N and NX are such that FC1>FC2. Consequently the rise in voltage levels at the nodes N and NX due to currents flowing via the p-channel transistors of the inverters 1a and 1b, accompanying the rise of the power supply voltage VDD, is slower on the side of the capacitor FC1 with larger capacitance, and faster on the side of the capacitor FC2 with smaller capacitance. As a result, a voltage difference is created between the nodes N and NX, and through the amplification action of the latch circuit 2, the L level and H level of the nodes N and NX prior to power supply interruption are restored. This operation is called “recall operation”.
Non-patent reference 1: T. Miwa et al, “A 512 kbit low-voltage NV-SRAM with the size of a conventional SRAM,” 2001 Symposium on VLSI Circuits, Digest of Technical Papers.
In the nonvolatile data holding circuit shown in FIG. 1, when the power supply voltage VDD is lower level, the transistor leakage currents of the inverters 1a and 1b cause the ferroelectric capacitors FC1 and FC2 to be charged. Hence the voltages at the nodes N and NX are determined by the charging leakage currents and by the capacitances of the ferroelectric capacitors FC1 and FC2. Here a leakage current charging a capacitor is the difference between the p-channel transistor leakage current and the n-channel leakage current. This transistor leakage current differs greatly due to distribution in threshold voltages. For example, when the threshold voltage scattering is dVth=80 mA, the leakage current is different by nearly one order.
Hence depending on scattering in the threshold voltages of the transistors comprised by the latch circuit, the H level and L level may be inverted in the recall operation. Scattering in threshold voltages depends on device fabrication processes, and cannot easily be reduced.
In order to resolve this problem, the applicant previously submitted patent applications, proposing improved nonvolatile data holding circuits using ferroelectric capacitors. One such example is Japanese Patent Laid-open No. 13-400507 (filed Dec. 28, 2001). In this improved version, a transistor for activation is provided on the power supply side of the latch circuit, and in recall operation, initially the plate line PL is driven, voltages are generated at the pair of storage nodes of the latch circuit according to the polarization directions of the ferroelectric capacitors, and thereafter the activation transistor is driven to activate the latch circuit, the voltage difference between the storage nodes is amplified, and the original data is latched.
In this improved version, a pair of ferroelectric capacitors are connected to each of the storage nodes of the latch circuit, two plate lines are driven to store data when interrupting the power supply, and when the power supply is turned on, one of the plate lines is driven to recall the data. The difference in capacitances of the pair of ferroelectric capacitors can be utilized to generate a large voltage difference between the storage nodes of the latch circuit through the recall operation.
However, in this improved version, when the two plate lines are driven in the store operation, coupling noise between the ferroelectric capacitors may cause the levels of the pair of storage nodes of the latch circuit to be inverted. Transistor connection capacitances, wiring capacitances, and other parasitic capacitances are connected to the storage nodes; but the capacitances of the ferroelectric capacitors are extremely large compared with these parasitic capacitances. Hence the effect of the above coupling noise is great, and consequently the storage node levels fluctuate considerably so that the data of the latch circuit may be inverted, and failure in writing data to the ferroelectric capacitors may occur.
The above problems are prominent when the size of transistors in the latch circuit is decreased and the current driving capacity is reduced in order to raise integration densities, and when there exists an imbalance in the performance of the inverters of the latch circuit or an imbalance in the parasitic capacitances of the storage nodes.